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62414nk 20140611-s00002/60214nk no.a2333-1/29 semiconductor components industries, llc, 2014 june, 2014 http://onsemi.com LV5685PV overview the LV5685PV is a multiple output linear regulator ic, which allows reduction of quiescent current. the LV5685PV is specifically designed to address automotive info tainment systems power supply requirements. the LV5685PV integrates 5 linear regulator outputs, 2 high side power switches, i 2 c-bus communication, acc detection, battery voltage detection, over-current limiter, overvoltage protection and thermal shut down. supply for v dd and sw33v outputs is low voltage specification, which enables drastic reduction of power dissipation compared to the existing model. function ? low consumption current: 65 a (typ, only v dd output is in operation) ? 5 regulator outputs v dd for microcontroller: output voltage: 3.3v, maximum output current: 350ma for system: output voltage: 3.3/5v(set by i 2 c-bus), maximum output current: 450ma for audio: output voltage: 5/8.5/9/11.5v(set by i 2 c-bus), maximum output current: 250ma for illumination: output voltage: 5/8/10.5/12v(set by i 2 c-bus), maximum output current: 300ma for cd: output voltage: 5/6/7/8v(set by i 2 c-bus), maximum output current: 1300ma ? 2 high side switches ext: maximum output current: 350ma, voltage difference between input and output: 0.5v ant: maximum output current: 300ma, voltage difference between input and output: 0.5v ? acc detection circuit detection voltage 2.7/3.2/3.6/4.2v (set by i 2 c-bus) ? battery voltage detection (bdet) : v cc 2 low voltage detection(uvdet): detection voltage 6/7/7.8/9v(set by i 2 c-bus) over voltage detection(ovdet): detection voltage 18v ? flg output cmos output of acc-detection/uvdet/ovdet/ovp ? i 2 c-bus communication interface each output except v dd is independently enabled/disabled. ilm/cd/audio/acc/uv voltage setting. read back supported: output voltage settin g, output over-current , flg(acc/uv/ ovdet/ovp) ? supply input v6in: 6v for v dd , system(sw33v) v cc 1: for internal reference voltage, control circuitry in case of voltage drop of v6in, v cc 1 supplies v dd output. v cc 2: for audio/ilm/cd/ext/ant ? over-current protection ? overvoltage protection(ovp): v cc 1, v cc 2 typ 23v (all outputs except v dd are turned off) ? thermal shutdown: typ 175c orderin g numbe r : ena2333a ordering information see detailed ordering and shipping informa tion on page 29 of this data sheet. hzip15 bi-cmos lsi system power supply ic for automotive infotainment multiple-output linear voltage regulator * i 2 c bus is a trademark of philips corporation.
LV5685PV no.a2333-2/29 specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage vcc max v6in max vcc1,vcc2 v6in 36 7 v input voltage vio max sda,scl,flg accin 7 36 v allowable power dissipation pd max ta 25c -independent ic -al heatsink (50 * 50 * 1.5mm 3 ) is used -size of heatsink: infinite 1.3 5.3 26 w peak supply voltage vcc peak vcc1/vcc2/accin ? see the test waveform below 50 v operating ambient temperature topr -40 to +85 c storage temperature tstg -55 to +150 c junction temperature tjmax +150 c ? waveform of surge test (vcc1,vcc2,accin) ? allowable power dissipation derating curve stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. 50v 16v 10% 90% 100ms 5msec (a) independent ic (b)aluminum heat-sink (50501.5mm3) heat-sink tightening condition tightening torque: 39n?cm , with silicone grease
LV5685PV no.a2333-3/29 recommended operating conditions at ta = 25 c vcc1 parameter conditions ratings unit operating supply voltage1 vdd output 7 to 16 v vcc2 parameter conditions ratings unit operating supply voltage2 ilm(10.5v) output ilm(8v) output 12.5 to 16 10 to 16 v operating supply voltage3 audio(8.5v) output 9.5 to 16 v operating supply voltage4 cd(8v) output(io=1.3a) cd(8v) output(io 1a) 10.5 to 16 10 to 16 v operating supply voltage5 ex t output, ant output 7.5 to 16 v v6in parameter conditions ratings unit operating supply voltage6 vdd output 5.1 to 6.5 v sw33v(3.3v) output 5.1 to 6.5 v sw33v(5v) output 5.7 to 6.5 v ? "maximum rating" and "recommended operating range" (*1) each lower limit value is determi ned by "output voltage"-"dropout voltage". (*2) operating in vcc1 vdd current path functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility. 36v 16v vcc1 ilm vcc2 23v 14v 12.5v 10v 7.5v vo=12v vo=10.5v vo=8v vo=5v 7v a udio 9.5v 7.5v vo=11.5v vo=9v vo=8.5v vo=5v 12.5v 10v cd(io 1a) 8v 7.5v vo=8v vo=7v vo=6v vo=5v 9v 10v 7.5v ext a nt out-o f -rating vdd sw33 7v 5.7v 6.5v vdd (io 0.16a) v6in disabled(ovp) recommended operation range operating1 operating2(*1) drop out re g ion 22.5v vo=5v vo=3.3v 5.1v 5.1v v6det (*2)
LV5685PV no.a2333-4/29 electrical characteristics at ta = 25 c(*1), vcc1=vcc2=14.4v, v6in=6v parameter symbol conditions min typ max unit quiescent current icc vdd w/out load, v6in=0v, accin=0v i 2 c register gr0/gr1/gr2=00h 65 100 a vdd output (3.3v) output voltage vo1 io1=200ma 3.13 3.3 3.47 v output current io1 vo1 3.1v 350 ma line regulation ? vo ln 1 5.7v160ma, or output voltage may be dropped when v6in voltage is decreased to approximately "v6in detection voltage". sw33v output (3.3v/5v) ; sw33_en=1 output voltage1 vo21 io2=200ma, sw_v=0 3.13 3.3 3.47 v output voltage2 vo22 io2=200ma, sw_v=1 4.75 5.0 5.25 v output current io2 vo21 3.1v, vo22 4.7v 450 ma line regulation ? vo ln 2 5.7v LV5685PV no.a2333-5/29 continued from preceding page. parameter symbol conditions min typ max unit cd output (5-8v); cd_en=1 output voltage1 vo41 io4=1000 ma , cd_v[1:0]=00 4.75 5.0 5.25 v output voltage2 vo42 io4=1000 ma, cd_v[1:0]=01 5.7 6.0 6.3 v output voltage3 vo43 io4=1000 ma , cd_v[1:0]=10 6.65 7.0 7.35 v output voltage4 vo44 io4=1000 ma, cd_v[1:0]=11 7.6 8.0 8.4 v output current io4 vo41 4.7v, v44 7.6v 1300 ma line regulation ? vo ln 4 vo+2v < vcc2 < 16v,io4=1000ma 50 100 mv load regulation ? vo ld 4 10ma LV5685PV no.a2333-6/29 continued from preceding page. parameter symbol conditions min typ max unit under-voltage detection(uvdet) detection voltage1 vuv1 vcc2 falling, uvd_v[1:0] =00 5.82 6.0 6.18 v detection voltage2 vuv2 vcc2 falling, uvd_v[1:0] =01 6.79 7.0 7.21 v detection voltage3 vuv3 vcc2 falling, uvd_v[1:0] =10 7.56 7.8 8.04 v detection voltage4 vuv4 vcc2 falling, uvd_v[1:0] =11 8.73 9.0 9.27 v release voltage1 vuvr1 vcc2 rising, uvd_v[1:0]=00 6.06 6.25 6.43 v release voltage2 vuvr2 vcc2 rising, uvd_v[1:0]=01 7.13 7.35 7.57 v release voltage3 vuvr3 vcc2 rising, uvd_v[1:0]=10 8.05 8.3 8.55 v release voltage4 vuvr4 vcc2 rising, uvd_v[1:0]=11 9.40 9.7 9.99 v detection hysterisis1 vuvhs1 uvd_v[1:0]=00 0.25 v detection hysterisis2 vuvhs2 uvd_v[1:0]=01 0.35 v detection hysterisis3 vuvhs3 uvd_v[1:0]=10 0.5 v detection hysterisis4 vuvhs4 uvd_v[1:0]=11 0.7 v over-voltage detection(ovdet) detection voltage vovd vcc2 rising 17 18 19 v detection hysterisis vodhys 0.5 v over-voltage protection(ovp) detection voltage vovp vcc1/vcc2 rising, output disabled 23 v detection hysterisis vovhys 0.5 v v6in shutdown detection(v6sdn) detection voltage v6sdn v6in falling, output disabled 0.6 1.02 1.4 v detection hysterisis v6sdhs 80 mv flg output flg "h" voltage vflgh isource=1ma vdd-0.3 vdd v flg "l" voltage vflgl isink=1ma 0.3 0.4 v i 2 c-bus i/f; scl,sda input "l" voltage v il 0 0.4 v input "h" voltage v ih 2.8 3.3 5.5 v sda "l" voltage v ol isink=1ma, ack or data read 0.3 0.4 v (*1) all the specification is defined based on the tests performed under the conditions where tj and ta(=25c) are almost equal. these tests were performed with pulse load to minimize the increase of junction temperature (tj). (*2) guaranteed by design product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
LV5685PV no.a2333-7/29 typical characteristics vcc=7v vcc=16v vcc=14.4v 125c 85c 25c -40c
LV5685PV no.a2333-8/29 v6in=5.3v v6in=6v v6in=6.5v v6in=5.3v v6in=6v v6in=6.5v 25c 85c 125c -40c
LV5685PV no.a2333-9/29 v6in=5.3v v6in=6v v6in=6.5v 25c -40c 85c 125c v6in=5.3v v6in=6v v6in=6.5v vcc2=12.5v vcc2=14.4v vcc2=16v
LV5685PV no.a2333-10/29 vcc2=16v vcc2=14.4v vcc2=12.5v 25c -40c 85c 125c vcc2=14.4v vcc2=16v vcc2=10v -40c 25c 85c 125c vcc2=10v vcc2=14.4v vcc2=16v
LV5685PV no.a2333-11/29 vcc2=16v vcc2=9.5v vcc2=14.4v -40c 25c 85c 125c vcc2=9.5v vcc2=14.4v vcc2=16v -40c 25c 85c 125c vcc2=7.5v vcc2=14.4v vcc2=16v
LV5685PV no.a2333-12/29 vcc2=7.5v vcc2=14.4v vcc2=16v -40c 25c 85c 125c
LV5685PV no.a2333-13/29 i 2 c-bus interface timing parameter symbol min typ max unit scl clock frequency fscl 0 400 khz start condition hold time thd;sta 0.6 us scl ?l? pulse-width tlow 1.3 us scl ?h? pulse-width thigh 0.6 us data hold time thd;dat 0 us data setup time tsu;dat 0.1 us sda/scl rise time tr 0.3 us sda/scl fall time tf 0.3 us stop condition setup time tsu;sto 0.6 us bus free time between stop and start condition tbuf 1.3 us bus line load capacitance cb 400 pf tbuf scl k sda tlow tf tr st thd;sta thd;dat thigh tsu;dat tf tr sp st tsu;sto
LV5685PV no.a2333-14/29 i 2 c bus interface format (msb first) this part is i 2 c controlled power supply, using 2 wires of scl,sda. the communication protocol comprises start-condition, dev ice-address, sub-address, data and stop-condition. every 8bits are followed by ack bit, and the receiver device pulls down sda line during ack period. this part doesn't accept sub-addr ess auto increment format. (single data byte write per a communication.) the protocol in read-mode comprises start-condit ion, device-address, dat a1, data2 and stop-condition. (note)the i 2 c-bus communication may be unstable when vdd voltage is not stable or out of s pecification range, since i 2 c-bus circuitry is supplied by vdd. ? device address s6 s5 s4 s3 s2 s1 s0 r/w 0 0 0 1 0 0 0 1/0 ? register map write d7 d6 d5 d4 d3 d2 d1 d0 init pm ilm_en cd_en audio_en sw33_en ext_en ant_en 00000000 vctl ilm_v1 ilm_v0 cd_v1 cd_v0 aud_v1 aud_v0 sw_v 00000000 det acc_v1 acc_v0 uvd_v1 uvd_v0 flgmd1 flgmd0 00000000 read d15 d14 d13 d12 d11 d10 d9 d8 init vctl ilm_v1 ilm_v0 cd_v1 cd_v0 aud_v1 aud_v0 sw_v v6det 00000000 d7 d6 d5 d4 d3 d2 d1 d0 init flg accuv uv ov ovp v6sdn oc 0 0 00000000 write mode scl sda start condition device address + r/w + ack data(address a) + ack read mode scl sda start condition device address + r/w + ack read data2 + ack stop condition read data1 + ack ak r d15 d14 d13 d12 d11 d10 d9 d8 ak d7 d6 d5 d4 d3 d2 d1 d0 ak s3 s6 s5 s4 s3 s2 s1 s0 stop condition sub address(a) + ack ak w a7 a6 a5 d7 d6 d5 a4 a3 a2 a1 a0 ak d4 d3 d2 d1 d0 ak s6 s5 s4 s2 s1 s0
LV5685PV no.a2333-15/29 write register explanation adr bit name init description 00h 7 ilm_en 0 ilm output enable 1: on 0: off 6 cd_en 0 cd output enable 1: on 0: off 5 audio_en 0 audio output enable 1: on 0: off 4 sw33_en 0 sw33 output enable 1: on 0: off 3 ext_en 0 ext output enable 1: on 0: off 2 ant_en 0 ant output enable 1: on 0: off 1 0 0 0 adr bit name init description 01h [7:6] ilm_v[1:0] 00 ilm output voltage(*) 11: 12v 10: 10.5v 01: 8v 00: 5v [5:4] cd_v[1:0] 00 cd output voltage(*) 11: 8v 10: 7v 01: 6v 00: 5v [3:2] aud_v[1:0] 00 audio output voltage(*) 11: 11.5v 10: 9v 01: 8.5v 00: 5v 1 sw_v 0 sw33v output voltage(*) 1: 5v 0: 3.3v 0 0 (*) "output voltage setting" is only valid when corresponding out put is set disabled(xxx_en=0). it is ignored when the output is set enabled(xxx_en=1). adr bit name init description 02h [7:6] acc_v[1:0] 00 acc detection volt age 11: 4.2v 10: 3.6v 01: 3.2v 00: 2.7v [5:4] uvd_v[1:0] 00 uvdet detection volt age 11: 9v 10: 7.8v 01: 7v 00: 6v [3:2] flgmd[1:0] 00 flg output mode 11/10: bdet only 01: acc only, 00: acc/bdet 1 0 0 0 read register explanation adr bit name init description [15:14] ilm_v[1:0] 00 ilm output voltage 11: 12v 10: 10.5v 01: 8v 00: 5v [13:12] cd_v[1:0] 00 cd output voltage 11: 8v 10: 7v 01: 6v 00: 5v [11:10] aud_v[1:0] 00 audio output voltage 11: 11.5v 10: 9v 01: 8.5v 00: 5v 9 sw_v 0 sw33v output voltage 1: 5v 0: 3.3v 8 v6det 0 v6indet / supply for vdd 1: v6in 0: vcc1 7 accuv 0 acc detection 1: under voltage 0: nornmal 6 uv 0 under voltage detection 1: under voltage 0: normal 5 ov 0 over voltage detection 1: over voltage 0: normal 4 ovp 0 over voltage protection 1: over voltage protection 0: normal 3 v6sdn 0 v6in shutdown detection 1: v6in shutdown 0: v6in applied 2 oc 0 output over current 1: over current 0: normal 1 0 0 0
LV5685PV no.a2333-16/29 package dimensions unit : mm hzip15 case 945ab issue a xxxxxxxxxx ymddd xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* soldering footprint* note: the measurements are not to guarantee but for reference only. through hole area package name hzip15 (unit: mm) *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 1.2 2.54 2.54 2.54 (1.91) 2.54
LV5685PV no.a2333-17/29 application circuit example peripheral parts part name description recommended value note c1,c2 capacitor for ext/ant output stabilization greater than 2.2 f c3,c4,c5, c10,c13 output stabilization capacitor greater than10 f(*1) c7,c9,c12 capacitor for bypass power supply c7: greater than 100 f c9,c12: greater than 47 f make sure to implement close to vcc and gnd. c6,c8,c11 capacitor for oscillation protector greater than 0.22 f d1,d2,d3,d4 internal device protection diode on semiconductor sb1003m3 d5 reverse current protection diode on semiconductor sb1003m3 (*1) make sure that output capacitors are greate r than 10uf and meets the condition of esr=0.001 to 10 ? , in which voltage/temperature dependence and unit differences are taken into consideration. moreover, in case of electrolytic capacitor, high-frequency characteristics should be sufficiently good. ilm accin cd sda scl vcc2 vcc1 gnd vdd v6in sw33v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LV5685PV audio flg ant ext ant d1 d2 ext d4 d3 sda scl vdd ilm cd audio +b sw33v c8 c9 c12 c11 c10 flg acc c13 c2 c1 c7 c6 v6in c3 c4 c5 d5
LV5685PV no.a2333-18/29 block diagram v6det vdd - + 3 - + 5 a udio - + 6 14 vref a ccin flg vref vreg scl vdd 3.3v, 0.35a vref 1.25v 5.1v vcc1 i 2 c-bus ctl gnd tsd 5/8.5/9/11.5v, 0.25a v6in vcc2 sw33v 3.3v / 5v, 0.45a - + ilm 5/8 / 10.5/12v, 0.3a - + cd 5/6/7/8v, 1.3a ext vcc2-0.5v, 0.35a a nt ext ctrl ant ctrl vcc2-0.5v, 0.3a sd a 6v input tsd ovp ovp disable all outputs except vdd tsd disable all putputs 11 15 4 1 2 9 12 10 8 13 ovp 7 ovp uv uv ov ovp uv vdd - + sw33_en vref ilm_en vref cd_en vref audio_en vref ext_en ant_en power on reset ov ov ovdet uvdet bdet flgmd vreg a cc
LV5685PV no.a2333-19/29 timing chart note: the above values are obtained when typ. all the voltage setting are default values i 18v vcc1 sw33v output 2.7v 2.8v ilm_en=1 v6in cd_en=1 audio_en=1 sw33_en=1 ext_en=1 ant_en=1 ilm_en=0 cd_en=0 audio_en=0 sw33_en=0 ext_en=0 ant_en=0 vdd 6.25v 6v 3.8v i 2 c inputs (scl/sda) ext output ant output accin flg vcc2 vdd output ilm output cd output audio output initial settings 23v 22.5v 17.5v output enable settings ovdet uvdet ovp detect ovp release 1.0v output enable settings v6in lost 1.1v
LV5685PV no.a2333-20/29 functional description [standby mode] when vcc1 is applied, internal control circuitry is automatically reset and goes into stand-by mode. in stand-by mode, following functions are active. vdd(3.3v) output i 2 c-bus communication (except for "pm" register) over voltage protection(ovp)/u vdet/ovdet/acc detection/flg output thermal shutdown(tsd) [vcc1/vcc2/v6in] vcc1 supplies vdd and common circuitry such as reference voltage, internal control circuitry. so vcc1 input is necessary for any operation of this device. vcc2 is the supply for audio/ilm/cd/ext/ant outputs. LV5685PV has the tolerance value of 50v against vcc1/2 and accin peak surge voltage, but for more safety set design, adding power clamp, such as power zene r diode, on battery connected line is recommended in order to absorb applied surge. LV5685PV has no protection against battery reverse c onnection, so adding schottky diode is recommended to prevent a negative voltage. v6in is the supply for sw33v. v6in also supp lies vdd when v6in voltage exceeds 4.85v(typ). when vcc2 and v6in is applied, ilm/cd/audi o/sw33/ext/ant output can be set enable via i 2 c-bus. when v6in is lower than 1.1v(typ)(max:1.5v ), output enable command above can't be accepted. [controls] the functions of LV5685PV can be controlled via i2c bus. see "i2c bus interface format" term for details. [linear regulators] vdd output when vcc1 is applied, vdd output is active regard less of control states. when v6in is applied and the voltage exceeds 4.85v(typ), supply for vdd output switches from vcc1 to v6in in order to reduce power dissipation. see "vdd regulator circuit description" term for detail. sw33v/cd/audio/ilm output these outputs are individually enabled or disabled via i 2 c-bus. the voltage of each output can be selected via i 2 c-bus. these commands must be set prior to enabling corresponding output. if you change the voltage for these outputs, be sure to do it after the output is set disabled. in order to avoid unwanted output voltage chang e, each "output voltage setting" is accepted only when corresponding output is set disabled(xxx_en=0). t he "output voltage setting" is ignored if the output is set enabled(xxx_en=1). output voltage setting can be referred by reading via i 2 c-bus(vctl register). it is strongly recommended to read and check vctl register value just before se tting enable the output in order to avoid unwanted output voltage change even in case if communication error were to happen and incorrect voltage setting were written to the device. each regulator output limits output current if the output gets over-loaded condition. the limit current decreases as the output voltage gets lower, in order to reduce the stress applied to the device.
LV5685PV no.a2333-21/29 all regulators in LV5685PV are low dropout outputs, becau se the output stage of all regulators is p-channel ldmos. when you select output capacitors for linear regulators, you should consider three main characteristics: startup delay, transient response and loop stability. the capacitor values and type should be based on cost, availability, size and temperature constraints. tantalum, aluminum electrolytic, film, or ceramic capacitors are all acceptable solutions. however, attention must be paid to esr constraints. the aluminum electrolytic capacitor is the least expensive solution, but if the circuit operates at low temperatures (-25 to -40c ), both the value and esr of the capacitor will vary considerably. the capa citor manufacturer's datasheet usually provides this information. [high-side switches] ant and ext are high-side power switches connected to vcc2. these outputs are individually enabled or disabled via i 2 c-bus. each high-side switch limits output current if the out put gets over-loaded condition. the limit current becomes lower value, if the output voltage gets lo wer than 2.5v(typ) in order to reduce the stress applied to the device. if these outputs are connected to inductive load or loads which have different ground potential, protection diodes (d1-4) are necessary to prot ect the device from negative voltage. [current limiting] when the each output becomes in over load condition, the device limits the output current. all outputs are also protected against shor t circuit by fold back current limiter. if one of each output except vdd is in ov er-current condition, oc bit of flg register is set 1, which can be read via i 2 c-bus. [flg output] flg is the cmos level logic output which indicate s the combination of several detectors' results. flg output is set "high"(vdd voltage), if all the following conditions are satisfied. flgmd[1:0] conditions 00 01 10 or11 acc acc input voltage>acc detection threshold 3 3 ignored bdet vcc2 voltage >uvdet threshold 3 ignored 3 vcc2 voltage LV5685PV no.a2333-22/29 [detections] under voltage detection (uvdet) if the vcc2 voltage gets lower than set value (uvd_v[1:0]), under-voltage is detected and the uv bit of flg register is set 1, which can be read via i 2 c-bus. flg pin keeps "low" during uvdet condition except for at flgmd[1:0]=01. each output status keeps t he same condition even if uv is detected. over voltage detection (ovdet) if the vcc2 voltage exceeds 18v(typ), over-voltage is det ected and the ov bit of flg register is set 1, which can be read via i 2 c-bus. flg pin keeps "low" during ovdet cond ition except for at flgmd[1:0]=01. each output status keeps the same cond ition even if ov is detected. acc under voltage detection if the accin voltage gets lower than set va lue (acc_v[1:0]), the accuv bit of flg register is set 1, which can be read via i 2 c-bus. flg pin keeps "low" during accuv is detected if flgmd[1:0] is 00 or 01. each output status keeps the same condition even if accuv is detected. over voltage protection (ovp) if the voltage of vcc1 or vcc2 exceed 23v(typ), ovp is detected and the ovp bit of flg register is set 1, which can be read via i 2 c-bus. and all the outputs ex cept vdd are automatically turned off. when the voltage of vcc1 and vcc2 get lower than 22.5v(typ), ovp detection is released. but output voltages are not automatically restored, because once ov p is detected, pm register of i 2 c-bus is reset. flg pin keeps "low" during ovp condi tion except for at flgmd[1:0]=01. v6in shutdown detection if the v6in voltage decreases lower than 1.0v(typ), v6 in-shutown is detected and the v6sdn bit of flg register is set 1, which can be read via i 2 c-bus. and all the outputs except vd d are automatically turned off. output voltages are not automatically activated if v6in voltage is restored, because once v6in shutdown is detected, pm register of i 2 c-bus is reset. thermal shutdown to protect the device from overheating, a thermal shutdown circuitry is in cluded. if the junction temperature reaches approximately 175c(typ), all outputs are turned off regardless of control state. after the junction temperature drops below 145c(typ), vdd ou tput is automatically restored and i 2 c-bus control becomes available. the thermal shutdown circuit does not guarantee the protection of the final product because it operates out of maximum rating (exceeding tjmax=150c).
LV5685PV no.a2333-23/29 vdd regulator circuit description ? reverse current protection for battery voltage black-out there is no diode inside to prevent reverse current from vdd to vcc1. you have to add external circuit to hold vdd voltage under battery voltage black-out. there is a parasitic diode from vdd to vcc1, so insert a diode between vcc2 and vcc1 as shown figure below. vcc2 vin 7 v6det vref - + 8 13 v6in vcc1 to uc parasitic diode back-up capacito r reverse current protection vdd 11 vdd supply switching diagram v out_vdd i out_vdd input voltage input current vout/iout v6in 4.85v(typ) vcc1 i vdd_v6in i vdd _ vcc1 4.75v(typ) i vdd _ vcc1 i vdd_v6in v6det vref 11 - + 8 13 v6in vcc1 v out_vdd i out_vdd i vdd _ v6in i vdd _ vcc1 ? supply current switching vdd output is always in operation except under thermal shut down (tsd) condition. there are 2 supply inputs (vcc1/v6in) for this output. vcc1 is capable of high-voltage input such as car-battery. v6in is a low voltage input and can be supplied from external dc/dc converter in order to decrease power dissipation of the device. supply current path from vcc1 or v6in is automatically switched depending on v6in voltage. if v6in voltage exceeds 4.85v(typ), v6in supplies vdd output. output ripple may be occurred when supply switching. this ripple can be improved by using proper output capacitor. select appropriate capacitor suitable for your requirement.
LV5685PV no.a2333-24/29 pin description pin # pin name function equivalent circuit 1 ext ext output vcc2-0.5v/350ma 2 ant ant output vcc2-0.5v/300ma 3 ilm ilm output 5v~12v 4 audio audio output 5v~11.5v continued on next page. vcc2 gnd 9 1 7 vcc2 gnd 9 2 7 vcc2 gnd 180k ? 1k ? 7 4 9 22~60k ? vcc2 gnd 180k ? 1k ? 7 3 9 20.9~60k ?
LV5685PV no.a2333-25/29 continued from preceding page. pin # pin name function equivalent circuit 5 cd cd output 5v~8v/1.3a 6 accin acc detection input 7 vcc2 supply terminal 8 vcc1 supply terminal 9 gnd gnd 13 v6in supply terminal 10 scl i 2 c-bus clock input 11 vdd vdd output 3.3v/0.35a continued on next page vdd gnd 9 10 11 1k ? 8 vcc1 vcc1 vcc2 gnd v6in 8 13 9 7 gnd 6 9 90k ? 36~78k ? vcc2 gnd 180k ? 1k ? 7 5 9 33.3~60k ? gnd 11 vcc1 140k ? 230k ? 13 8 9
LV5685PV no.a2333-26/29 continued from preceding page. pin # pin name function equivalent circuit 12 sda i 2 c-bus data input 14 flg flg output 15 sw33v sw33v output 3.3v/5v 0.45a vdd gnd 9 11 12 1k ? 100 ? gnd 100 ? 9 14 11 vdd v6in gnd 230/420k ? 1k ? 13 15 9 140k ?
LV5685PV no.a2333-27/29 hzip15 heat sink attachment heat sinks are used to lower the semiconductor device junction temperature by l eading the head generated by the device to the outer environment and dissipating that heat. a. unless otherwise specified, for power ics with tabs and power ics with attached heat sinks, solder must not be applied to the heat sink or tabs. b. heat sink attachment ? use flat-head screws to attach heat sinks. ? use also washer to protect the package. ? use tightening torques in the ranges 39-59ncm(4-6kgcm) . ? if tapping screws are used, do not use screws with a diameter larger than the holes in the semiconductor device itself. ? do not make gap , dust, or other contaminants to get betwe en the semiconductor device and the tab or heat sink. ? take care a position of via hole . ? do not allow dirt, dust, or other contaminants to get between the semiconductor device and the tab or heat sink. ? verify that there are no press bu rrs or screw-hole burrs on the heat sink. ? warping in heat sinks and printed circuit boards must be no more than 0.05 mm between screw holes, for either concave or convex warping. ? twisting must be limited to under 0.05 mm. ? heat sink and semiconductor device should be mounted in parallel . take care of electric or compressed air screw driver ? the speed of these torque wrenches must not exceed 700 rpm, and should typically be about 400 rpm. binding-head machine-screw countersunk head machine screw gap heat sink via hole
LV5685PV no.a2333-28/29 c. silicone grease ? spread the silicone grease evenly when mounting heat sinks. ? sanyo recommends yg-6260 (mom entive performance materials japan llc) d. mount ? first mount the heat sink on the semiconductor dev ice, and then mount that assembly on the printed circuit board. ? when attaching a heat sink after mounting a semicondu ctor device into the printed circuit board, when tightening up a heat sink with the screw, the mechanical stress which is impossible to the semiconductor device and the pin doesn't hang. e. when mounting the semiconductor device to the heat sink using jigs, etc., ? take care not to allow the device to ride onto the jig or positioning dowel. ? design the jig so that no unreasonable mech anical stress is applied to the semiconductor device. f. heat sink screw holes ? be sure that chamfering and shear drop of heat sin ks must not be larger than the diameter of screw head used. ? when using nuts, do not make the heat sink hole di ameters larger than the diameter of the head of the screws used. a hole diameter about 15% larger than the diameter of the screw is desirable. ? when tap screws are used, be sure that the diameter of the holes in the heat sink are not too small. a diameter about 15% smaller than the di ameter of the screw is desirable. g. there is a method to mount the semiconductor device to the heat sink by using a spring band. but this method is not recommended because of possible displace ment due to fluctuation of the spring force with time or vibration.
LV5685PV ps no.a2333-29/29 ordering information device package shipping (qty / packing) LV5685PV-xh hzip15 (pb-free / halogen free) 20 / fan-fold on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liab ility arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use a s components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applica tion in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for an y such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and dis tributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona linjuryor death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale i n any manner.

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